In order for circuits within a computer system to easily communicate with other circuits, system busses were introduced. A system bus consists of multiple lines, including address lines, data lines, Read/Write or handshake lines and other control signal lines. System busses tend to be asynchronous in nature with the data signal lines sending the appropriate data to a device whose address is specified on the address lines, in response to handshake signals. For example, a bus would allow a Central Processing Unit (CPU) to read and write data into specific memory locations in a Random Access Memory (RAM).
The size of a system bus is dependent on the capabilities of the CPU which is used to control the system bus. Originally, system busses were as small as 4 bits in data width. As integrated circuit technology has improved, metal line widths and metal spacing within integrated circuits has decreased, allowing the width of a microprocessor's data bus to increase to 32 bits, which is commonly used in conjunction with current technology. In the future, data busses will grow wider, as the technology progresses.
As the width of data busses has increased, the width of the address bus used by present systems has also increased. A 32 bit address bus is now commonly used, giving a 32 bit microprocessor direct address space exceeding one gigabyte.
Due to the increase in the width of busses, additional pins are now required when designing an integrated circuit package which is to communicate with a microprocessor. As the number of pins has increased, due to the increase in the size of the system bus necessary, the costs of producing an integrated circuit have also increased to the point that the cost of the integrated circuit package now typically exceeds the cost of the fabricated die contained within. For these reasons, it has now become important to limit the number of pins required in an integrated circuit package by using individual pins for multiple functions in order to decrease costs and minimize the space required for the placement of the integrated circuit.
Integrated circuits in the prior art have time multiplexed address signals and data signals onto the same pins, using a single pin as an address pin during one period of time and then using the same pin as a data pin during a later period of time. Another method used to multiplex functions on a single pin is to have a pin function in one manner during the power up sequence of a system and then in a second manner during normal operation of the system. In other cases, a pin may function differently depending upon the mode or operating context of the integrated circuit.
Various microprocessor manufacturers have previously supported differing types of hand shake mechanisms. For example, the hand shake mechanism of the VME bus is supported by Motorola's 68XXX series of microprocessors and hand shaking of the ISA bus is supported by Intel's 8086, 80286 and 80386 microprocessors.
Bus types also differ in that they may be synchronous or asynchronous. Asynchronous busses use hand shake mechanisms to transfer data bus information between different circuits. The bus is asynchronous because it will operate at irregular intervals without reference to a central timing clock or source. Synchronous busses, on the other hand have a separate clock signal included as a part of the system bus which requires the circuits to perform operations in response to the common clock signal. Data transfer rates of synchronous busses are faster than asynchronous busses but the system bus is required to have a greater signal count because it includes the clock signal. In certain applications the clock signal can be increased to twice its previous value which also improves the data transfer rate of a synchronous bus.
Computer manufacturers have typically designed the internal computer system bus structure around the microprocessor that they support. Because each manufacturer supports its own microprocessor, numerous bus structures have been developed and become standards. IBM developed and uses the ISA bus standard for the IBM PC system bus structure, Apple Computer has developed and uses the NUBUS standard for the system bus structure of some Macintosh computers, Intel has developed and uses the PI bus standard and VESA (Video Electronics Standard Association) has developed and uses the Local Bus standard (VL Bus). Other known bus standards are SBus, Micro Channel, EISA Bus, Multibus 1, GIO Bus, Q22 bus and TURBOchannel. There are many other bus structures used within various electronic equipment, but most of these system busses have not become popular standards because the equipment is not used widely or the system bus is proprietary and is not disclosed.
Of interest herein are the computer system busses developed around Intel's family of microprocessors, including the ISA bus, the PI bus and the Local bus. However, it will become clear that the present invention can be applied to other bus structures as well.
The ISA bus standard is used in almost every IBM PC or PC clone and accordingly has become a very popular bus standard. The ISA bus standard was created by IBM and has a 16 bit wide data path and a 24 bit wide address bus. The ISA bus is asynchronous and originally operated with system clock rates of 8 MHz. Because the ISA bus standard has remained fixed, it has become limited for use in conjunction with modern high speed microprocessors.
The PI bus standard was created by Intel Corporation for use in notebook and laptop computers. The PI bus standard has power saving features as well as a faster bandwidth rate than the ISA bus standard. The PI bus standard also utilizes a 16 bit wide data bus and a 24 bit wide address bus.
The specifications for the Local (VL) bus standard were developed by the Video Electronics Standard Association (VESA). The Local bus has a higher data transfer rate than the ISA bus or the PI bus. The Local bus has a 32 bit wide data bus and a 32 bit wide address bus. The bus is synchronous and designed for a system clock rate of 33 MHz. The Local bus is designed such that a higher system clock rate can be utilized. The Local bus can be configured to run with a 16 bit or 32 bit wide data bus, depending on the microprocessor that is used. Similarly, the Local bus can also be configured to run with a 1X clock or a 2X clock, depending on the capabilities of the microprocessor.
Within the computer, boards and circuits that communicate with the bus have interface circuitry which supports the appropriate bus standard. For example IBM PC circuits would be specially designed to interface with an ISA bus that used an Intel microprocessor. Other circuits would be specially designed to interface with a local bus standard. These boards are usually connected to a mother board inside of a personal computer to add further flexibility and to facilitate expansion. Some of the more popular boards which can be added to a computer system are serial I/O, MODEM controller, VGA video controller, hard disk controller and ethernet interface cards. The functionality of many of these cards have now been integrated onto a single chip allowing individual chips to directly interface with the system bus, particularly in portable or laptop computers.
Integrated circuit designers have tried to design a single chip which supports multiple bus standards to allow system or board designers to design boards that adapted to the various bus standards, using the same integrated circuit. In addition, the ability to upgrade the system board by simply plugging in a new advanced microprocessor has been desired by board designers. In this manner the number of parts kept in inventory would decrease for board and integrated circuit manufacturer alike.
Integrated circuits of the prior art have provided some bus flexibility to a board designer by programming the bus type into the chip using resistors as illustrated in FIG. 1. The resistors 130 and 131 illustrate how a resistor can be soldered onto a circuit board to respectively pull-up and pull-down the input pins 106 and 107 of the integrated circuit 133. To pull up the input pin 106, the resistor 130 is coupled between the input pin 106 and the power supply VDD. To pull down the input pin 107, the resistor 131 is coupled between the input pin 107 and the ground GND. For connection to a different bus type, for example, the resistors 130 and 131 could be configured such that the resistor 130 would pull-down and the resistor 131 would pull-up the input pins 106 and 107, respectively.
Another hardware method used in the prior art to support multiple bus selections uses dip switches to select from a plurality of busses. Using dip switches to select a bus type allows greater flexibility than the soldering method, using resistors. Dip switches are typically available in packages which include multiple switches. For example, FIG. 1 illustrates a dip switch package 132 which includes the 8 dip switches 122-129. A dip switch has two positions, either the dip switch is off or the dip switch is on. In the ON position, the dip switch is closed, as illustrated by the dip switch 123. In the OFF position, the dip switch is open, as illustrated by the dip switch 122. In the configuration illustrated by FIG. 1, the input pins 108-111 of the integrated circuit 133 can be selectively pulled-up or pulled-down by appropriately opening or closing the dip switches 122-129. For example, the input pin 108 is pulled-down by closing the dip switch 123 and opening the dip switch 122. The input pin 109 is pulled-up by closing the dip switch 124 and opening the dip switch 125. In this manner, the four input pins 108-111 can be configured to select 16 different bus types.
Typically, two bus types have been supported within integrated circuits depending on the type of microprocessor used within the computer. The Intel 80X86 and the Motorola 68000 microprocessors have been the most used, but with the growing number of computer manufacturers, more specialized bus types have been developed around the different computer systems.
In another prior art method used within Rockwell's R65C29 microprocessor, a different microprocessor's handshake signals have been set up using registers. The host computer in this instance can be either Zilog Z80/Intel 8080 or Rockwell 6500/Motorola 6800 set by Bit 0 of the Host Control and Status Register (HCSR). In this instance the actual bus size did not increase because the interface remains at 8 data bits and 16 address bits. A disadvantage of this register method is that the microprocessor does not automatically recognize the bus type and adapt accordingly.
Some disadvantages to the hardware methods of the prior art are that the extra components use valuable board space, decrease system reliability and increase system costs. Another disadvantage is that power is consumed by these hardware methods from leakage currents. While this power consumption is not significant in circuit boards powered through an AC/DC power supply converter, it is likely to be significant in portable equipment. Because of the increase in miniaturization and portability it is desirable to eliminate these components to conserve critical space, increase reliability and reduce system costs. Eliminating or reducing the number of pull-down and pull-up resistors could decrease power consumption in portable equipment that relies on a self contained power supply such as a battery.
What is needed is an apparatus which eliminates the use of passive components such as dip switches and resistors within computer systems to select the interface to a particular bus system protocol. What is further needed is an apparatus which can automatically sense the bus system type interfacing to an integrated circuit, in order to correctly adapt to the protocol and physical properties of that bus. What is also needed is a way to more efficiently use the pins of an integrated circuit package and thereby reduce the costs associated with the integrated circuit package and to conserve board space. What is also needed is a way to reduce the power consumed by the integrated circuit package and to reduce costs by eliminating the storage of alternate inventory necessary to support multiple bus protocols.